| 摘要 |
Methods and apparatus are provided for decreasing soft errors and cell leakage in integrated circuit structures. The structures of the invention preferably include memory cells that utilize thin-film transistors ("TFTs") for the pull-up and pull-down transistors, and well as for the pass-gates. These TFTs preferably include features such as ion implants and a dielectric with a high dielectric constant "K." In addition to reducing soft errors and cell leakage, the invention preferably provides other benefits such as low cell area and scalability.
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