| 摘要 |
PROBLEM TO BE SOLVED: To construct a signal processing circuit by normal program data at all times. SOLUTION: When a video scope is connected to a processor, main configuration data are read from a memory and whether or not the data are normal is judged (S103). When they are normal, the main configuration data are written to an FPGA as they are (S104). On the other hand, when they are not normal, sub configuration data are read from the memory and whether or not the data are normal is judged (S109-S111). Then, when they are normal, the sub configuration data are written to the FPGA (S113). COPYRIGHT: (C)2008,JPO&INPIT
|
