| 摘要 |
In one embodiment, a Central Processing Unit having a processing core. The processing core connects to an internal memory bus having N address lines and X data lines. A cache connects to the internal memory bus and uses M of N bits of the N address lines to address data stored in the cache. A cryptographic unit in the CPU encrypts data written to an external memory and decrypts data read from the external memory. The cryptographic unit encrypts and decrypts N-M address lines of the internal memory bus and the data lines of the bus.
|
