| 摘要 |
A circuit ( 26 ) performs a discrete Walsh transform using a reduced set of arithmetic operators. The circuit ( 26 ) comprises a first memory component ( 32 ), an adder ( 36 ), a subtractor ( 38 ), a second memory component ( 40 ), and a controller ( 52 ). In each of a plurality of stages, the controller ( 52 ) enables the first memory component ( 32 ) to communicate each of a plurality of pairs of values stored therein to the adder ( 36 ) and to the subtractor ( 38 ). The controller ( 52 ) enables the second memory component ( 40 ) to store each of a plurality of results from the adder ( 36 ) and the subtractor ( 38 ) and to communicate the stored results to the first memory component ( 32 ) for use in a subsequent stage. In the subsequent stage, the controller ( 52 ) enables the first memory component ( 32 ) to communicate to the adder ( 36 ) and to the subtractor ( 38 ) a plurality of new pairs of data values consisting first of the add results from the previous stage in the order they were generated and then the subtract results in the order they were generated.
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