Method and apparatus for clock synthesis using universal serial bus downstream received signals,申请号EP20040250430-传众专利搜索

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发明名称	Method and apparatus for clock synthesis using universal serial bus downstream received signals
摘要
申请公布号	EP1445681(A3)	申请公布日期	2008.05.07
申请号	EP20040250430	申请日期	2004.01.27
申请人	STMICROELECTRONICS, INC.;AXALTO INC.	发明人	LEYDIER, ROBERT ANTOINE;POMET, CHRISTOPHE ALAIN
分类号	G06F1/04;G06F1/12	主分类号	G06F1/04
代理机构		代理人
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