发明名称 METHOD AND APPARATUS FOR INTEGRATED HIERARCHICAL ELECTRONICS ANALYSIS
摘要 A computer implemented method, apparatus, and computer usable program code for analyzing durability of electronic components. A finite element model for the chassis is created. A set of finite element models for a set of printed wiring assemblies are created, wherein the printed wiring assemblies are for use with chassis and include the electronic components. The finite element model for the chassis is combined with the set of finite element models to form a combined finite element model. A finite element analysis of the combined finite element model is performed to form results. The combined model results are transferred to the printed wiring board models. Using the transferred results, stresses and strains are calculated for individual solder joints/leads. A fatigue analysis is performed for the electronic components in the set of printed wiring assemblies based on these stresses and strains, using the results to identify the durability of the electronic components.
申请公布号 US2008104553(A1) 申请公布日期 2008.05.01
申请号 US20060549819 申请日期 2006.10.16
申请人 RASSAIAN MOSTAFA;TWIGG DAVID W;LEE JUNG-CHUAN 发明人 RASSAIAN MOSTAFA;TWIGG DAVID W.;LEE JUNG-CHUAN
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址