发明名称 Methods of applying read voltages in NAND flash memory arrays
摘要 Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.
申请公布号 US2008101122(A1) 申请公布日期 2008.05.01
申请号 US20060635995 申请日期 2006.12.08
申请人 KANG HYUNG-SEOK;HAN EUI-GYU;HAN GYEONG-SOO;LEE JIN-YUB;KIM HOO-SUNG 发明人 KANG HYUNG-SEOK;HAN EUI-GYU;HAN GYEONG-SOO;LEE JIN-YUB;KIM HOO-SUNG
分类号 G11C16/04 主分类号 G11C16/04
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