| 摘要 |
Provided is a semiconductor memory device in which it is possible to conduct a parallel test by comparison with an expected value after replacement with a redundant cell. A redundant circuit provided in correspondence with each of a plurality of redundant addresses includes a determination circuit for determining whether an access address has been replaced with a redundant cell, and a circuit for producing an activated output signal if a signal, which indicates that an area is using a redundant set, and a redundancy selection signal have both been activated. The memory device includes a logic circuit for outputting an activated redundant hit signal when at least one determination circuit of determination circuits corresponding to respective ones of a plurality of redundant addresses is activated; a logic circuit for outputting an activated signal when all outputs of the circuits are inactive; and a selector for outputting a test-result mask signal when a redundant area is tested, and outputting the output of the logic circuit when a normal area is tested. The test result is forcibly passed when a memory array is tested and when a redundant address is accessed.
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