| 摘要 |
An apparatus and a method for generating a clock using a piecewise linear modulation are provided to reduce power consumption by blocking a clock of a block which is not used. An apparatus for generating a clock using a piecewise linear modulation includes a modulation profile generation unit(360), a delta sigma modulator(370), a phase frequency comparison unit(310), a charge pump(320), a loop filter(330), a voltage controlled generator(340), and a fraction divider(350). The modulation profile generation unit outputs an M-bit digital value of which a piecewise linear modulation profile having a combination of at least two linear signals is quantized. The delta sigma modulator receives the M-bit digital value and outputs a K-bit value which is delta-sigma-modulated. The phase frequency comparison unit outputs an up-down pulse having the same phase difference with a phase difference between a reference clock and a feedback clock. The charge pump outputs a predetermined current for a corresponding time to the phase difference of the up-down pulse. The loop filter outputs a voltage controlled voltage corresponding to a predetermined current. The voltage controlled generator outputs a multi-phase clock of a frequency corresponding to the voltage controlled level. The fraction divider receives the multi-phase clock of the voltage controlled generator. The fraction divider selects a divider based on the K-bit value, and outputs the divided clock as the feedback clock.
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