发明名称 ACCELERATED MULTIPLIER UNIT BASED ON NEURONS
摘要 FIELD: computer engineering, possible use for synthesis of arithmetical and logical devices, for creating fast action and highly productive digital devices which realize the function of multiplication in direct codes. ^ SUBSTANCE: multiplier contains data input block, multiplicand register block, multiplier register block, addition block, decoder block, result storage block, control block. In multiplier unit, multiplication of binary numbers is performed. The sign of result of multiplication is determined by modulo two addition of signs of multiplicand and multiplier. The operation of multiplication is realized by analyzing lower bits of multiplier, shifting the multiplier for two bits to the right, shifting the multiplicand to the left. The result of multiplication of numbers is produced as a total of partial results of multiplication. ^ EFFECT: increased speed of operation, increased reliability of operation, simplification of algorithm of operation of device control block. ^ 11 dwg
申请公布号 RU2322688(C2) 申请公布日期 2008.04.20
申请号 RU20060110815 申请日期 2006.04.03
申请人 GOSUDARSTVENNOE OBRAZOVATEL'NOE UCHREZHDENIE VYSSHEGO PROFESSIONAL'NOGO OBRAZOVANIJA "KURSKIJ GOSUDARSTVENNYJ TEKHNICHESKIJ UNIVERSITET" 发明人 KOBELEV NIKOLAJ SERGEEVICH;LOPIN VJACHESLAV NIKOLAEVICH;KOBELEV VLADIMIR NIKOLAEVICH;SHEVELEVA ELENA SERGEEVNA;FETISOVA EVGENIJA VLADIMIROVNA;SHEVELEV SERGEJ STEPANOVICH
分类号 G06F7/52 主分类号 G06F7/52
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