发明名称 TIMING DIAGRAM EDIT PROGRAM, RECORDING MEDIUM, TIMING DIAGRAM EDIT DEVICE AND TIMING DIAGRAM EDIT METHOD
摘要 PROBLEM TO BE SOLVED: To raise quality and efficiency of hardware design verification by describing an interface protocol using intuitively understandable mathematical descriptions. SOLUTION: A timing diagram is displayed on a GUI of a timing diagram edit device. Then input of numerical information which represents iteration counts of a waveform image for the arbitrary number of clock among the displayed timing diagram is received, and based on input numerical information, the iteration counts of the waveform image is decided. Then, a sequence image where the waveform image in the timing diagram is replaced with a continuous waveform image which is a connection of the waveform images for the number of iterations is displayed on the GUI. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008083780(A) 申请公布日期 2008.04.10
申请号 JP20060260338 申请日期 2006.09.26
申请人 FUJITSU LTD 发明人 IWASHITA HIROAKI
分类号 G06F17/50 主分类号 G06F17/50
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