| 摘要 |
PROBLEM TO BE SOLVED: To quickly eliminate influence of jitter in a clock signal while suppressing circuit size of a sampling frequency converting apparatus. SOLUTION: The sampling frequency converting apparatus 30 produces data DA2 synchronized to a clock signal LRCKb from data DA1 to be sequentially supplied by synchronizing to a clock signal LRCKa. A latch circuit 325 outputs spacing (a) between timing to be designated by the clock signal LRCKa and timing to be designated by the clock signal LRCKb. An interpolation ratio specifying unit 327 specifies an interpolation ratio (Fa) in response to output from the latch circuit 325. An interpolating unit 34 holds data DA1 as data train for operation by sequentially acquiring with a timing to be specified by the clock signal LRCKa, and data DA2 are produced by sequentially performing interpolation calculation in response to the interpolation ratio (Fa) and the data train for calculation by making the interpolation calculation synchronize to the clock signal LRCKb. COPYRIGHT: (C)2008,JPO&INPIT
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