| 摘要 |
An integrated circuit 2 includes processing pipeline stages formed of an input register 8 , processing circuit 10', 10'' and an output register 12 . The output register 12 employs speculative sampling and uses a subsequent speculation period during which any change in its input is detected and used to indicate a speculation error. In order to reduce the chances of a race condition giving rise to a false positive detection of a speculation error due to a too rapid signal propagation through the processing circuitry 10', 10'' , a transparent latch 14 is disposed at the approximate midpoint, measured in terms of propagation delay, within the processing circuitry 10', 10'' . This transparent latch 14 is non-transmissive during the speculation period of the output register 12 so as to prevent any new signal propagating from the input register 8 during the speculation period from reaching the output register 12.
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