| 摘要 |
Provided is a pipe latch circuit of a multi-bit pre-fetch type semiconductor memory device with an advanced structure. The pipe latch circuit includes: a first latch circuit for simultaneously latching K-bit input data (K is an integer), which is received by simultaneously pre-fetching from an internal core circuit through global input/output lines, in response to an input latch control signal; a first multiplexing circuit for selecting K/2-bit input data among K-bit input data in response to a first selection control signal; a second multiplexing circuit for selecting 2-bit input data among the K/2-bit input data in response to a second selection control signal; and a second latch circuit for alternately latching the 2-bit data to sequentially output the latch data as output data in response to output latch control signals. The invention cuts down the overall chip size and current consumption of the pipe latch circuit by reducing the number of multiplexers necessary for arranging the pre-fetched data in a predetermined output order.
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