| 摘要 |
A low-frequency circuit tester tests a high-frequency circuit to determine whether the circuit will operate properly at its specified operating frequency when clocked by a clock signal having a specified period. Each of the first and second phases of the test spans the same number of test cycles, with each test cycle spanning a uniform period exceeding the specified clock period. During each of first and second phases of the test, the circuit tester transmits the same input signal patterns to the circuit and monitors output signal patterns produced by the circuit in response to the input signals. The tester also provides a clock signal for clocking the circuit's logic. During odd-numbered test cycles of the first phase of the test and even-numbered test cycles of the second phase of the test, the tester supplies a pulse of a clock signal to the circuit with a first delay following to the start of the test cycle. During even-numbered test cycles of the first phase of the test, and odd-numbered test cycles of the second phase of the test, the tester supplies a pulse of the clock signal to the circuit with a second delay following the start of the test cycle. The tester adjusts the first and second delays so that if the circuit passes both phases of the test, a test engineer will be able to infer that the circuit will operate at its specified operating frequency.
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