发明名称 CIRCUIT DESIGN SUPPORT SYSTEM, CIRCUIT DESIGN SUPPORT METHOD AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To solve the problems that, in focusing only a path of the largest delay to improve a delay value, the delay of the other path is increased and a series of the flow including behavioral synthesis, delay analysis and operation level description improvement are not completed at all as a result, when coping with the delay after the behavioral synthesis in circuit design utilizing the operation composition. SOLUTION: When displaying a behavior level description corresponding to a plurality of delay paths selected by a designer, the corresponding part of the behavior level description is displayed to reflect the number of paths to be affected in altering the behavior level description or changing the method of the behavioral synthesis. Thus, since the designer can clearly specify a part where the delay of the entire circuit can be efficiently handled in the behavior level description, a series of the flow including the behavioral synthesis, the delay analysis and the behavior level description improvement is quickly completed. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008077490(A) 申请公布日期 2008.04.03
申请号 JP20060257365 申请日期 2006.09.22
申请人 NEC CORP 发明人 HARUTA YASUMICHI
分类号 G06F17/50 主分类号 G06F17/50
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