发明名称 Method of Fabricating Semiconductor Device Having Dual Stress Liner
摘要 A method of fabricating a semiconductor device comprising providing a substrate including a PMOS region and an NMOS region forming a PMOS gate electrode on the PMOS region and an NMOS gate electrode on the NMOS gate region, respectively, forming a stress liner on the PMOS region formed with the PMOS gate on the PMOS region and the NMOS region formed with the NMOS gate electrode on the NMOS region, and selectively applying radiation onto the stress liner formed on either one of the PMOS region and the NMOS region in an inert vapor ambiance.
申请公布号 US2008081406(A1) 申请公布日期 2008.04.03
申请号 US20070750491 申请日期 2007.05.18
申请人 CHOO JAE-OUK;YOON II-YOUNG;NAM SEO-WOO;KOO JA-EUNG 发明人 CHOO JAE-OUK;YOON II-YOUNG;NAM SEO-WOO;KOO JA-EUNG
分类号 H01L29/739 主分类号 H01L29/739
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