发明名称 |
Method and apparatus for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications |
摘要 |
Methods and apparatus are provided for automatic rate identification and channel synchronization in a master-slave setting for high data throughput applications. An interface is provided for use between a parallel bus and a serial bus. The interface includes a plurality of serializer/deserializer circuits that generate a clock signal, wherein one of the serializer/deserializer circuits is a master circuit generating a master clock signal and the remaining of the serializer/deserializer circuits are slave circuits generating slave clock signals. The master clock signal is substantially phase-aligned to a reference clock and is distributed to the slave circuits. The interface also includes a clock divider associated with the master circuit for selectively generating a master clock signal having one or more lower data rates than the reference clock; and a frequency detector associated with each of the slave circuits for automatically detecting a rate of the master clock signal.
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申请公布号 |
US2008080600(A1) |
申请公布日期 |
2008.04.03 |
申请号 |
US20060541398 |
申请日期 |
2006.09.29 |
申请人 |
DAI XINGDONG;SINDALOVSKY VLADIMIR |
发明人 |
DAI XINGDONG;SINDALOVSKY VLADIMIR |
分类号 |
H04L5/16;H04L7/00 |
主分类号 |
H04L5/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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