| 摘要 |
A matrix multiplication processor (1) for multiplying a first matrix with a second matrix to form an output matrix, each matrix comprising a plurality of elements in rows and columns, the matrix processor comprising: a memory (2) having a first area in which, in use, the first matrix is stored, a second area in which, in use, the second matrix is stored and a third area to which, in use, the output matrix is written, an accumulator (4) having an input and arranged to, in use, store a running total and add values at its input to the running total; a multiplier (3) having an input for two values and an output and arranged to, in use, multiply two values at its input and output the product of the two values at its output; and a control unit (5) arranged to control the operation of the matrix multiplication processor; in which the control unit is arranged, such that in use, it repeatedly chooses (102) an element from the first matrix and an element from the second matrix, causes the elements thus chosen to be passed (104) to the multiplier (3) and causes (106) the resultant product to be passed to the accumulator (4) to be added to the running total; wherein the elements of each matrix are stored, in use, in sequential memory locations of the respective memory area in row-wise and/or column- wise order; and in which the control unit selects the elements from the first and second matrix by moving stepwise (112-130) through the first and second memory areas. Also, a processing apparatus comprising a first processor (11) and a second processor (1) connected by a data bus (10), in which the first processor (11) is a general-purpose processor and the second processor (1) is more efficient than the first at calculating matrix multiplication. The processors thus disclosed may advantageously be used in video processing situations, such as road lane detection from vehicles. |
