| 摘要 |
Disclosed is a signal processor including a serial-to-parallel converter inputting serial digital video signals for n channels and converting the serial digital video signals for respective channels into parallel digital video signals. The signal processor further includes a frame-synchronization scrambler scrambling predetermined bits of the parallel digital video signals and storing the initial values in the auxiliary data section as auxiliary data; and a self-synchronization scrambler scrambling the parallel digital data for respective channels; and a multiplexer multiplexing the parallel digital data for respective channels. The signal processor still further includes a multi-channel forming unit obtaining a predetermined number of bits from the parallel digital data and forming serial digital data for m channels; and a data-multiplexing parallel-to-serial converter generating serial digital data by multiplexing and converting the serial digital data for m channels formed by the multi-channel data forming unit. |
