| 摘要 |
Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of signals of the user design, and for each set of signals, generates a respective supplement of a subset of the user design supplementing the subset with a logic analyzer coupled to the set of signals. The compiler generates a respective configuration for each supplement. The selector selects a configuration or multiple configurations responsive to the specified set of signals and the sets of signals. The PLD implements the user design after the PLD is programmed with the selected configuration or configurations. The monitor accesses the specified set of signals in the PLD via the logic analyzer corresponding to each of the selected configuration or configurations.
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