发明名称 Power network synthesizer for an integrated circuit design
摘要 A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the simplified plans are evaluated to select a plan that conforms to a user-specified limit for an attribute, such as maximum voltage drop. The selected simplified plan, which identifies a total count of power wires and a width of the power wires, is used in a second stage to prepare a more detailed plan that honors the design rule checking constraints and routing blockages. The detailed plan is evaluated to check for conformance with the user-specified limit on the attribute, and if necessary the detailed plan is changed, e.g. by increasing wire width one or more times, to achieve conformance.
申请公布号 US7353490(B2) 申请公布日期 2008.04.01
申请号 US20040976411 申请日期 2004.10.29
申请人 SYNOPSYS, INC. 发明人 JIANG YI-MIN;TAI PHILIP HUI YUH;KWON SUNG-HOON
分类号 G06F17/50 主分类号 G06F17/50
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