发明名称 ALALOG MEMORY
摘要 An analog memory is provided to reduce the number of second MOS transistors connected to a discharge line per one line, by dividing the discharge line into plural lines. A first, a second and a third memory block comprise a plurality of capacitors maintaining charges according to an input signal, an output line transmitting the charges and a plurality of MOS transistors(Min,Mout) switching connection state of the capacitor and the output line. When the capacitor and the output line are sequentially connected and a signal is outputted from the output line to a buffer circuit in the first memory block, all connections between the capacitor and the output line are interrupted in the second and the third memory block. And the output line in the first memory block is connected to the output line in the second memory block.
申请公布号 KR20080028810(A) 申请公布日期 2008.04.01
申请号 KR20070096767 申请日期 2007.09.21
申请人 SANYO ELECTRIC CO., LTD.;SANYO SEMICONDUCTOR COMPANY LIMITED 发明人 ONAYA MASATO;SERIZAWA SHUNSUKE
分类号 G11C7/10;G11C7/16 主分类号 G11C7/10
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