| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of correcting a circuit without changing a chip size by arranging a multi-logic cell below power supply wiring. SOLUTION: In a semiconductor device formed of automatic arrangement wiring employing a standard cell by a multi-layer process, the multi-logic cell is arranged below second metal power supply wiring whereby a layout which permits the change of a circuit without changing the chip size or a lower stage layer by arranging the multi-logic cell below the second metal power supply wiring is made. COPYRIGHT: (C)2008,JPO&INPIT
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