发明名称 |
Mechanism to generate logically dedicated read and write channels in a memory controller |
摘要 |
According to one embodiment, a system is disclosed. The system includes a memory controller to schedule read commands to frames via a first dedicated command slot and to schedule write commands and corresponding data to frames via a dedicated second or third command slot.
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申请公布号 |
US2008077761(A1) |
申请公布日期 |
2008.03.27 |
申请号 |
US20060528774 |
申请日期 |
2006.09.27 |
申请人 |
SUBASHCHANDRABOSE RAMESH;MOHANTY ANUPAM;AGARWAL RAJAT |
发明人 |
SUBASHCHANDRABOSE RAMESH;MOHANTY ANUPAM;AGARWAL RAJAT |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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