| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a delay locked loop circuit for supplying a stable clock signal. <P>SOLUTION: In the delay clock loop circuit, a voltage control delay line circuit has a delay element with two or more steps and generates a multi-phase clock from clock as a reference. In a phase comparison circuit, a phase difference of first and second clocks, in which the outputs of first-stage and final-stage delay elements are each converted to a single waveform, is obtained. In a charge circuit and discharge circuit, charge current and discharge current are generated in a time duration corresponding to the phase difference. In a correction circuit, a difference of the charge current and discharge current is held at a prescribed value. A low pass filter has a capacity for generating a first control voltage through charge/discharge with charge current or discharge current. A second control voltage generation circuit generates a second control voltage so that the first control voltage may be turned into a prescribed voltage. In the voltage control delay line circuit, the first and second control voltages for controlling the multi-phase clock generation means are applied so that a phase difference between the first and second clocks is kept constant. <P>COPYRIGHT: (C)2008,JPO&INPIT |
