| 摘要 |
PROBLEM TO BE SOLVED: To provide a memory interface circuit preventing an incorrect latch operation of a data signal, even when deterioration or mismatch occurs in transmission conditions. SOLUTION: A memory interface circuit 21, having oscillator circuit 50, delay circuit 16, phase comparator 60 and data latch 17, can be connected to a DDR-SDRAM 11 which outputs a DQS signal 12 and a data signal 13 in synchronization with a clock. After delaying a clock being output from the oscillator circuit 50, the delay circuit 16 outputs the delayed clock as a read clock 53. The phase comparator 60 measures a phase difference between an input data strobe signal 57 and the read clock 53. The delay circuit 16 adds or subtracts the delay time of the read clock 53 according to the measured phase difference. The data latch 17 fetches the data signal 13 in synchronization with the read clock 53. COPYRIGHT: (C)2008,JPO&INPIT
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