MULTILAYER CHIP CAPACITOR

摘要

A multilayer chip capacitor is provided to realize sufficiently reduced ESL(Equivalent Series Inductance) and to be used for decoupling in a power circuit. A multilayer chip capacitor includes a main body(101), a plurality of inner electrode layers, at least one first outer electrode, and at least one second outer electrode. The main body is formed by stacking a plurality of dielectric layers and has opposite first and second lateral surfaces(B1,B2) and opposite third and fourth lateral surfaces(C1,C2). The plurality of inner electrodes is stacked and separated by the dielectric layers in the main body. At least one outer electrode is formed on the first lateral surface. At least one second outer electrode is formed on the second lateral surface. The first and second outer electrodes are spaced apart at a predetermined interval in a longitudinal direction of the first lateral surface and are arranged to be offset each other.