Integrated circuit device with on-chip setup/hold measuring circuit

摘要

An integrated circuit device disclosed herein includes a test device and a setup and hold measuring circuit. The setup and hold measuring circuit generates a reference signal and a data signal in response to an external clock signal in a test mode of operation. The test device receives the data signal in response to a reference signal, and outputs the inputted data signal as a setup and hold determining circuit. One of the reference signal and the data signal is a multiphase signal synchronized with the external clock signal. The setup and hold measuring circuit detects whether the output of the test device indicates a valid value of the data signal, and generates the detected result to the external as a setup/hold timing margin through at least one pad.