| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase adjustment circuit which is obtained with a small circuit scale without using a high frequency clock and performs phase adjustment with finer resolution, and to provide a phase-locked loop circuit. <P>SOLUTION: A horizontal synchronizing signal SYNC_IN to be inputted is shifted by a phase shift circuit 21 in response to the value of the high-order 2 bits of a phase adjustment data CKPHASE. An up/down counter 22 up/down-counts the clock NCKP, based on the shift output. The count result is outputted to a latch circuit 23 by way of a multiplying circuit 32, etc. The latch circuit 23 performs latching by a pulse ENCKP for data enabling, so as to output a phase adjustment output HD_SIG. <P>COPYRIGHT: (C)2008,JPO&INPIT |
