发明名称 VARIABLE DELAY APPARATUS
摘要 PROBLEM TO BE SOLVED: To provide a variable delay apparatus wherein even immediately after a change of delay amount of the variable delay apparatus, no signals that have different timings from a set delay amount are output. SOLUTION: The variable delay apparatus comprises a variable delay block 108 that includes N delay elements 101a-101n and N selectors 102a-102n where N is a natural number; a variable delay block 109 that includes N delay elements 103a-103n and N selectors 104a-104n; and a selector 107. After output signals of the variable delay blocks 108, 109 have become to exhibit the output timings of set delay amounts after selection signals 105a-105n, 106a-106n are changed, the signals to be output by the selector 107 are switched, thereby avoiding any signals having timings different from the timing of a delay amount set for the output signal from being output immediately after the change of the delay amount. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008067352(A) 申请公布日期 2008.03.21
申请号 JP20070163978 申请日期 2007.06.21
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AOYANAGI HIDEKI;ASANO HITOSHI;TOKI KAZUYA;MATSUO MICHIAKI;FUJITA TAKU
分类号 H03K5/13 主分类号 H03K5/13
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