| 摘要 |
PROBLEM TO BE SOLVED: To make it possible to deal with a change in a delay amount caused by a rapid change in PVT characteristics during system high-load operation or the like. SOLUTION: A phase adjustment circuit adjusts phases of a data signal and a data strobe signal supplied from an external circuit utilizing a clock delay adjustment circuit 100 for supplying an output clock signal delayed for an input clock signal by adjusting a phase of the input clock signal when performing write and/or read access on an external storage means. The phase adjustment circuit comprises an internal storage means for writing write data and/or read data therein, an internal storage means for recording the value of a delay parameter of the clock delay adjusting circuit when a timing margin is ensured in write and/or read access, an optimum value calculating means for calculating an optimal value of the timing margin, and an optimal value storage means for recording the optimal value of the timing margin. COPYRIGHT: (C)2008,JPO&INPIT
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