| 摘要 |
A shift register, including first through third output nodes and first through third input lines for first through third clock signals, a fourth input line adapted to supply a start pulse or an output signal, a voltage level controller coupled between the second and fourth input lines, the voltage level controller being adapted to control voltage levels of the first and second output nodes, a first transistor coupled between a first power supply and the third output node, the third output node being an output node of the stage, a second transistor coupled between the third output node and the third input line, and a third transistor coupled between the first output node and a second power supply.
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