| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To shorten a processing time and improve power-saving effect, using a relatively simple configuration. <P>SOLUTION: An information processing system includes a bus 1; a plurality of bus masters 2-0 to 2-2; a plurality of bus slaves 3-0, 3-1; a bus arbitration circuit 20 for receiving a plurality of bus right request signals req 0 to req 2, from the bus masters 2-0 to 2-2 via the bus 1 and grants a bus right to one of the bus masters 2-0 to 2-2 by arbitrating the conflict from among the bus right request signals req 0 to req 2; a bus right detection circuit 20 for detecting the number of the plurality of bus right request signals req 0 to req 2 to output the number of detection; and a clock frequency dividing circuit 30. The circuit 30 frequency-divides a reference clock clk 0 by a plurality of frequency-dividing values that differ in size, to generate frequency-dividing signals of a plurality of frequencies that differ in size, and selects the frequency-dividing signal of a frequency of the size that corresponds to the size of the number of the detection to output an operation clock clk 1. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
