| 摘要 |
A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.
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