| 摘要 |
<P>PROBLEM TO BE SOLVED: To planarize simply an interlayer film on the upper electrode of a capacitor related with the miniaturization of DRAM having a stacked capacitor. <P>SOLUTION: A DRAM cell transistor 302, a first interlayer film 303, and a first contact plug 304, are formed on a silicon substrate 301. An etching stopper film 305 and a second interlayer film 306, a third interlayer film 307, a fourth interlayer film 308, and a fifth interlayer film 315, are formed on the first interlayer film 303. A lower part opening 309 and an upper part opening 310 are formed, a lower electrode 311 of a capacitor, a capacitance insulating film 312, and an upper part electrode 313 are formed in the opening of the interlayer film. Moreover, a side wall 314 composed of the same material as the lower electrode 311 is formed in the region contacting the fourth interlayer film 308 in the side of the upper electrode 313. <P>COPYRIGHT: (C)2008,JPO&INPIT |
