FREQUENCY-MULTIPLYING DELAY LOCKED LOOP AND METHOD FOR GENERATING AN OUTPUT CLOCK SIGNAL USING ITS,申请号KR20017013919-传众专利搜索

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发明名称	FREQUENCY-MULTIPLYING DELAY LOCKED LOOP AND METHOD FOR GENERATING AN OUTPUT CLOCK SIGNAL USING ITS
摘要
申请公布号	KR100811766(B1)	申请公布日期	2008.03.10
申请号	KR20017013919	申请日期	2001.10.30
申请人		发明人
分类号	H03L7/00	主分类号	H03L7/00
代理机构		代理人
主权项
地址

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