| 摘要 |
A circuit is disclosed having a first series circuit path including a first switching transistor, a cascode transistor disposed in cascode arrangement with the first switching transistor, a transformer, and a fourth switching transistor. The circuit also has a second series circuit path having a second switching transistor, the transformer, and a third switching transistor. Both the first series circuit path and the second series circuit path are coupled between a first voltage source and a second voltage source. The cascode transistor has a bias applied to a port thereof for limiting current flowing therethrough.
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