| 摘要 |
A low dropout voltage regulator ( 100; 300 ) comprises a supply input terminal ( 102; 302 ) for connecting a supply voltage (V<SUB>DD</SUB>) and an output terminal ( 104; 304 ) for providing a regulated output voltage (V<SUB>0</SUB>), a reference voltage source ( 130; 330 ); and an output voltage monitor ( 120; 320 ). An error amplifier ( 132; 332 ) has an output ( 138; 338 ) supplying an error signal (V<SUB>err</SUB>) in response to deviations of the regulated output voltage (V<SUB>out</SUB>) from a desired target output voltage value (V<SUB>0</SUB>) at the output terminal ( 104; 304 ). A power output FET ( 110; 310 ), has a drain-source channel connected between the supply input terminal ( 102; 302 ) and the output terminal ( 104; 304 ) of the voltage regulator, and a gate terminal ( 116; 316 ). The gate terminal of the power output FET ( 110; 310 ) is controlled by the error amplifier ( 132; 332 ) via a driver FET ( 140; 340 ) in such a way that any deviations of the regulated output voltage (Vout) from a desired target output voltage value (V<SUB>0</SUB>) are minimized. The regulator further comprises a bypass FET ( 150; 350 ) of an n-conductivity type, which has a source terminal ( 154; 354 ) connected to the gate terminal ( 142; 342 ) of the driver FET ( 140; 340 ), a drain terminal ( 156; 356 ) connected to the source terminal ( 112; 312 ) of the driver FET ( 140; 340 ), and a gate ( 152; 352 ) connected to a bias voltage source ( 158; 358 ). The bias voltage is determined such that the bypass FET ( 150; 350 ) begins conducting when the source voltage of the driver FET ( 140; 340 ) cannot be further reduced by application of the error signal (V<SUB>err</SUB>) to its gate towards the drain potential, due to the inherent gate-source voltage drop (V<SUB>gs</SUB>) of the driver FET ( 140; 340 ).
|
