| 摘要 |
A method for modifying instances of a repeating pattern in an integrated circuit design to correct for perturbations during rendering is described. In the typical embodiment, these corrections are optical proximity corrections that correct for optical effects during the projection of the mask pattern onto the wafer and/or processing effects for example photoresist response and etching effects. The method comprises determining a correction for the repeating pattern based on a first set of tolerances for features of the repeating pattern. Then, the suitability of the corrections is evaluated for instances of the repeating pattern in the integrated circuit design based on a second set of tolerances, which is different from the first set of tolerances. This can be used to preserve much of the hierarchy of the layout data in the corrected, or lithography, data. This can be achieved during the OPC process, thus avoiding the post OPC compaction. It can further take advantage of the fact that, for a given physical layer of a chip for example, different portions of the representing design polygons typically have different requirements on pattern fidelity on the wafer while perturbations may vary as a function of field position. By applying knowledge of the feature tolerances, and allowing design corrections only when tolerances are not met, the data explosion that occurs when moving from layout to lithography data can be contained without sacrificing accuracy.
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