发明名称 Page buffer circuit and method for multi-level NAND programmable memories
摘要 A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.
申请公布号 US7336538(B2) 申请公布日期 2008.02.26
申请号 US20060495874 申请日期 2006.07.28
申请人 STMICROELECTRONICS S.R.L. 发明人 CRIPPA LUCA;MISSIROLI CHIARA;RAVASIO ROBERTO;MICHELONI RINO;BOVINO ANGELO
分类号 G11C16/04 主分类号 G11C16/04
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