发明名称 |
Dual gate transistor keeper dynamic logic |
摘要 |
A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
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申请公布号 |
US7336105(B2) |
申请公布日期 |
2008.02.26 |
申请号 |
US20050168692 |
申请日期 |
2005.06.28 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHUANG CHING-TE;KIM KEUNWOO;KUANG JENTE BENEDICT;NOWKA KEVIN JOHN |
分类号 |
H03K19/20;H01L21/84;H03K19/094 |
主分类号 |
H03K19/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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