发明名称 CLOCKED STANDBY MODE WITH MAXIMUM CLOCK FREQUENCY
摘要 <p>A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a period of the first clock signal is less than a period of the second clock signal and the voltage generator is selectively enabled in conjunction with the second clock signal when the period of the second clock signal is less than the period of the first clock signal.</p>
申请公布号 KR100807423(B1) 申请公布日期 2008.02.25
申请号 KR20060069236 申请日期 2006.07.24
申请人 发明人
分类号 H03K17/00 主分类号 H03K17/00
代理机构 代理人
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