发明名称 Analog switch circuit and sample-and-hold circuit including the same
摘要 First and second analog switches are connected in series between first and second nodes. One terminal of a third analog switch is connected to a series connection node of the first and second analog switches. The other terminal of the third analog switch is supplied with a second voltage different from a first voltage applied to the first node. The third analog switch drives on when the first and second analog switches drive off, and outputs the second voltage to the series connection node of the first and second analog switches.
申请公布号 US7332941(B2) 申请公布日期 2008.02.19
申请号 US20050088557 申请日期 2005.03.14
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 ISHII HIROTOMO
分类号 G11C27/02;H03M1/12;H03K17/00;H03K17/06;H03K17/687;H03K17/73;H03M1/66 主分类号 G11C27/02
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