摘要 |
A power semiconductor device having high avalanche capability comprises an N<SUP>+ </SUP>doped substrate and, in sequence, N<SUP>- </SUP>doped, P<SUP>- </SUP>doped, and P<SUP>+ </SUP>doped semiconductor layers, the P<SUP>- </SUP>and P<SUP>+ </SUP>doped layers having a combined thickness of about 5 mum to about 12 mum. Recombination centers comprising noble metal impurities are disposed substantially in the N<SUP>- </SUP>and P<SUP>- </SUP>doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N<SUP>- </SUP>doped epitaxial layer on an N<SUP>+ </SUP>doped substrate, forming a P<SUP>- </SUP>doped layer in the N<SUP>- </SUP>doped epitaxial layer, forming a P<SUP>+ </SUP>doped layer in the P<SUP>- </SUP>doped layer, and forming in the P<SUP>- </SUP>and N<SUP>- </SUP>doped layers recombination centers comprising noble metal impurities. The P<SUP>+ </SUP>and P<SUP>- </SUP>doped layers have a combined thickness of about 5 mum to about 12 mum.
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