DELAY LOCKED LOOP AND METHOD OF GENERATING DELAY SIGNALS FOR REDUCING THE NUMBER OF DELAY CELLS

摘要

A delay locked loop and a delay signal generating method are provided to decrease a switching noise and a size of the DLL(Delay Locked Loop) by decreasing the number of delay cells in the DLL. A delay locked loop includes a delay line(210) and a phase-frequency detector(220). The delay line sequentially delays an input signal and generates N/2 delay signals and corresponding inverted signals. The delay line outputs one of the delay and inverted signals corresponding to a duty ratio of an input signal as a comparison signal. The phase-frequency detector compares phases and frequencies of the comparison signal with a current input signal and outputs a control signal based on the compared result. When the duty ratio of the input signal is 50%, the delay line outputs the inverted signal corresponding to the N/2-th delay signal to the phase-frequency detector.