| 摘要 |
A semiconductor memory device is provided to shorten data read time by decreasing line capacitance and junction capacitance of a data input/output line. A memory cell array comprises a plurality of memory cells at the crossing point of a word line and a bit line. A data cache array is arranged on a data cache array region and comprises a data cache maintaining data read-out from the memory cell temporarily. A shunt region has a contact connecting the word line or a signal line with another metal line as being formed on the memory cell array region. An extended region is formed with the shunt region extended on the data cache array region. A plurality of data input/output lines is arranged to transmit data of the bit line through the data cache array at the same time. A plurality of read circuits is connected to the plurality of data input/output lines.
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