| 摘要 |
A semiconductor memory device providing a VPP voltage and a VBB voltage consistently is provided to provide the VPP voltage and the VBB voltage to a sub array block or a bit line sense amplifier block uniformly. According to a semiconductor memory device(200) comprising a bit line sense amplifier and a memory cell array block including a number of sub array blocks(210_1,210_2), a first metal-1 layer contacts with a first high density P type doped region in the bit line sense amplifier block. At least one metal-2 layer contacts with the first metal-1 layer. At least one second metal-1 layer contacts with the metal-2 layer. A third metal-1 layer is located at the boundary of the sub array block and the bit line sense amplifier block, and supplies a boosting voltage to the sub array block. A back bias voltage(VBB) applied to the first metal-1 layer is supplied to the sub array block or the bit line sense amplifier block through the metal-2 layer and the second metal-1 layer.
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