| 摘要 |
A semiconductor integrated circuit device includes a first memory cell coupled to a first WL and one of a pair of BLs for information bits, a second memory cell coupled to the first WL and one of a pair of BLs for parity bits, a third memory cell coupled to a second WL and the other of the pair of BLs for information bits, a fourth memory cell coupled to the second WL and the other of the pair of BLs for parity bits, column switches which connect the pair of complementary BLs for parity bits to a pair of data lines for parity bits, and a logic correction circuit connected to one of the pair of data lines for parity bits. The logic correction circuit executes a parity bit rewrite operation.
|
