| 摘要 |
A delay locked loop circuit and a jitter reducing method thereof are provided to decrease an amount of bang-bang jitters in the DLL(Delay Locked Loop) by mixing two delay signals around a middle point between first edges of the delay signals. An auxiliary phase shifter(31) receives a clock signal and outputs a clock signal with or without a delay. A coarse delay line(32) receives an output signal from the auxiliary phase shifter, sequentially delays the received signal, and outputs plural delay signals. A phase selector(33) selects two of the delay signals and outputs the selected signals. A phase mixer(34) phase-mixes the two delays signals and outputs a feedback signal. A phase detector(35) compares the clock signal with the feedback signal and generates a detection signal corresponding to a phase difference between the clock signal and the feedback signal. A control circuit(36) controls the auxiliary phase shifter, the phase selector, and the phase mixer in response to the detection signal. |
